Flash memory data is stored as a variable amount of charge on a secondary gate that floats between a conventional gate and a channel. The amount of charge on this floating secondary gate changes the effective threshold voltage (Vt) of the cell and results in a variable current for a fixed top gate voltage (Vg). In conventional flash sensing schemes used in 90 nm and 65 nm process technology, a fixed current (Ids) is applied to measure the cell threshold voltage Vt and the gate voltage Vg determines a cell state.
In a multi-level cell (MLC) approach utilizing two-bit cell memory, the wordline (WL) ramps through three different levels to sense the four possible combinations of two bits in cell states 00, 01, 10, 11. Ramping to each level consumes time in the sensing process.
It is desirable to have an improved scheme for faster access time. At the same time, having a better reference for sensing by reduction of 1/f or Random Telegraph Signal (RTS) noise is also desired.